1. Technical Field
The present invention relates to clock signal control for integrated circuits, and more-particularly, to method and system for propagating a clock control signal across a chip.
2. Description of Related Art
During the manufacture of digital integrated circuits, it is essential that the integrated circuit be tested to ensure that it matches the functional specification and that only defect-free production chips are packaged and shipped to the customer. After the chips have been manufactured, an external testing machine may be used to determine whether there are any defects in the chip. As the density of circuitry on a chip continues to increase with advances in technology and as the number of input/output pins remains small, testing becomes more complex and more costly.
Today, design for testing is a large portion of the chip design. Certain portions of the chip may be dedicated only for testing. Level-Sensitive Scan Design (LSSD) is a design technique used for designing test circuits on a chip. LSSD imposes strict rules on clock signal usage to allow the implementation of sequential scan latches for testing the circuit. LSSD is commonly known in the art and provides rigid clocking rules in order to prevent data input to the scan latches from changing while the clock pulse is transitioning. Thus, the digital circuit is comprised of two sections: (1) a combinational circuit; and (2) a set of sequential scan latches used to test the circuit. The latches are used such that during testing the value of each latch may be individually controlled and observed by shifting (i.e., scanning) a serial vector into/out of the scan latch. Because the latches inside the circuit are effectively input/output terminals, the testing of the circuit is simplified while maintaining a small number of input-output pins on the chip. The LSSD technique allows more inputs/outputs for testing the circuit than are actually available at the boundary of the chip.
When using LSSD techniques, it is necessary to supply a test clock and test controls to operate the chip in a test mode. Currently, a separate clock distribution system is used to distribute the clock and control signals to the scan latches. Thus, instead of having only one H-tree clock distribution system, for example, the integrated circuit contains at least two H-tree clock distribution systems. One is for the high-performance clock which is used to drive the functional or dynamic logic on the chip, and one is used to drive the test logic.
It is desirable to test a chip xe2x80x9cat speed,xe2x80x9d i.e., the normal operating speed of the chip. When tested in this manner, defects which only arise at the normal operating speed of the chip can be detected by the test circuitry. The problem with testing the chip at speed is that as clock speeds increase on chips, the complex balancing of timing between the system clock tree and the test clock tree becomes even more difficult and costly. Furthermore; the expensive testing equipment currently used to test the chips cannot be operated at the same speed as the system clock. Thus, the chip must be tested in the manufacturing environment at a speed lower than that at which it would normally operate. The problem with testing at a lower speed is that all of the defects in the chip may not show up at the lower test speed. Therefore, the customer may actually be the first one to learn of a defect when the chip is put into operation.
Thus, a method and system for testing is needed which allows the chip to be tested at speed while also allowing the expensive test equipment which is currently in use to be utilized to perform such testing. It is also desirable to require only one tightly tuned high speed clock distribution system because of the added complexity and increased wiring that results from the use of multiple clock distribution systems.
The present invention avoids the need for multiple clock distribution systems by allowing clock controls for clock stopping, scanning, and debugging to be distributed to all local clock buffers through pipelined non-scan latches. The test control pipeline latches may be routed along with the clock through the clock receiver, the central clock buffer, and the sector buffer areas of the chip. A relatively low speed testing mechanism may be used to drive the testing of the chip externally. The test clock control signals are synchronized with a free-running clock on the chip to allow the circuit to be operated at speed during the testing of the chip.